Engine timer

ABSTRACT

Disclosed is a timer for indicating the average timing of an internal combustion engine. The timer includes a duty cycle generator which produces a series of pulses whose duty cycle varies with the average timing of the engine. These pulses are fed through a filter to produce an analog signal for display by a conventional voltmeter or ammeter.

finite States atent U91 Pottebaum [1 11 asaez Aug. 27, E974 ENGINE TIMER[75] Inventor: Joseph R. Pottebaum, Columbus,

Ohio

[73] Assignee: Production Measurements Corporation, Hilliard, Ohio [58]Field of Search 324/15, 16 R, 16 T, 83 A, 324/83 D; 73/116-119 [56]References Cited UNITED STATES PATENTS 3,697,865 l0/l972 Smith 324/16 TPrimary ExaminerMichael J. Lynch Attorney, Agent, or Firm-LeBlanc & Shur[57] ABSTRACT Disclosed is a timer for indicating the average timing ofan internal combustion engine. The timer includes a duty cycle generatorwhich produces a series of pulses whose duty cycle varies with theaverage timing of the engine. These pulses are fed through a filter toproduce an analog signal for display by a conventional voltmeter orammeter.

18 Claims, 9 Drawing Figures [O J OSCILLATOR )[6 L I2 I28 REFERENCE DUTYr VOLTAGE CYCLE FILTER SOURCE GENERATOR [a SPARK U 20 M DAMPER cPAIENIEflmcznQu SIIHSNS FIG] SPARK I8 I H L D 50 MS AT I200 RPM ENGINETIMER This invention relates to an internal combustion engine timer andmore particularly to an average timer for improving the timing ofinternal combustion engines such as automobile engines. It provides arelatively simplified and inexpensive timer particularly adapted for useby automotive dealers and repair shops where the investment ofsubstantial sums of money in more complicated equipment is notwarranted.

In a four-cycle engine of the type customarily employed in automobileseach cylinder fires once for every two revolutions of the crank shaft.In most engines, a spark is provided for each cylinder slightly prior tothe top dead-center position for the piston on its compression stroke,although engines are occasionally designed to fire after the topdead-center position.

Firing is controlled by a timing system. This includes a distributorhaving a rotating shaft coupled to the crank shaft by a 2:1 gearingmechanism whereby the distributor shaft makes one complete rotation forevery two crank shaft rotations. The distributor shaft carries amulti-lobe cam (one lobe for each cylinder) which engages with afollower to operate a set of breaker points. These are shunted by acapacitor in a primary circuit of a spark coil connected to the battery.Opening of the points as the timing cam rotates provides rapid magneticfield changes in the secondary of the spark coil with resulting highvoltage across the coil secondary. The high voltage pulses are coupledto individual spark plugs by a rotating contact member carried by thedistributor shaft and engaging with a series of fixed contacts in thedistributor, each connected to one of the spark plugs.

Timing is normally adjusted in relation to the top dead-center positionof the No. 1 piston by rotating a plate carrying the cam follower andbreaker points in relation to the cam on the distributor shaft.

Accurate engine timing is extremely important because an improperlytimed engine operates inefficiently and with less than optimum power andalso because timing errors increase the octane requirement of the fuel.Also of increasing importance is the fact that an improperly timedengine produces high exhaust emissions and consequent air pollution.

The normal procedure employed in engine timing utilizes a timing lightwhich has a stroboscopic lamp fired by discharge of the No. l sparkplug. Firing of the lamp illuminates a pointer mounted on the engine inrelation to a dial on the rotating damper pulley. The recurringmomentary illumination of the pointer and dial indicates therelationship between the firing of the No. 1 cylinder and the topdead-center position of its piston, ordinarily in terms of degreesbefore (or after) topdead center.

The foregoing system possesses several disadvantages. First, because ofthe positioning of the various measuring components, there can besubstantial and unpredictable parallax in reading of the pointer andmarkings on the damper pulley, thereby rendering the measurementinaccurate. Moreover, the stroboscopic timing equipment itself possessesinherent inaccuracies, due to the dynamic nature of the operation, andthe visual nature of the observations. Further, measurements have beenmade with reference to a single cylinder on the assumption that eachcylinder actually fires in precisely fixed relationship to the No. 1cylinder. However, inperfections in the timing gears, the cam andelsewhere in the timing mechanism can cause deviations as much as i 3from the designed values. Thus, if the cam surface for cylinder No. l isinaccurate, the resulting offset may completely invalidate the timingreading. Even if the No. 1 cylinder is adjusted to fire exactly asspecified, for example at 6 before top deadcenter, adjustment of thetiming for the No. 1 cylinder to achieve this ordinarily results infiring the remaining cylinders anywhere between 3 and 9 before topdeadcenter. This is totally unacceptable, particularly in view ofincreasing demand for reduced exhaust emissions.

In order to overcome these and other disadvantages there is disclosed inassignees copending US. Pat. application Ser. No. 219,416, filed Jan.20, 1972, a method and apparatus for measuring the average timing ofinternal combustion engines. In that application there is disclosed adigital technique for producing a series of pulses whose number isrepresentative of average engine timing and counting the number ofpulses during a timing interval to give an indication of engine timing.

The present invention is directed to an average engine timer of the samegeneral type as that disclosed in the above-mentioned copendingapplication but one that is of more simplified and less expensiveconstruction. In the present invention pulses derived from a spark coilpickup and a damper pickup are applied to a duty cycle generator. Theduty cycle generator varies the duty cycle of pulses from a relativelyhigh frequency oscillator in proportion to engine timing as determinedby the angular distance between the spark and damper pulses. These highfrequency pulses having a duty cycle representative of average enginetiming are applied to a filter to produce an analog voltage or currentused to drive an analog display in the form of a conventional voltmeteror ammeter. The output from the duty cycle generator is substantiallyindependent of frequency and therefore of engine speed so that in thepresent invention it is not necessary to accurately control engine rpmin order to provide an accurate output reading. The result is anaccurate and yet simplified and inexpensive device which does notrequire a large investment of time and money to operate and is suitablefor use by automotive dealers, repair shops and others who may not wishto make a large investment in engine timing equipment.

It is therefore one object of the present invention to provide animproved internal combustion engine timer.

Another object of the present invention is to provide a simplified andless expensive average timer for internal combustion engines.

Another object of the present invention is to provide an average timerfor internal combustion engines incorporated an analog display.

Another object of the present invention is to provide an improved andsimplified average timer particularly adapted for timing automotiveengines.

Another object of the present invention is to provide an average timerfor internal combustion engines which eliminates the necessity forclosely controlling engine speed in order to provide an accurate readingof engine timing.

Another object of the present invention is to provide an average timerfor internal combustion engines in which the duty cycle of a relativelyhigh frequency electrical signal is varied in accordance with enginetiming.

Another object of the present invention is to provide an improved methodof obtaining average engine tim- These and further objects andadvantages of the invention will be more apparent upon reference to thefollowing specification, claims and appended drawings wherein:

FIG. 1 is a simplified block diagram of an average timerconstructed inaccordance with the present invention;

FIG. 2 is a detailed circuit diagram of the filter and meter forming theanalog display portion of the average timer of FIG. 1;

FIG. 3 is a more detailed block diagram of the digital portion of thetimer of FIG. 1;

FIG. 4 is an overall circuit diagram of the digital portion of the timerillustrated in FIG. 3;

FIG. 5 is a wave form diagram showing the count pattern of the sparkcounter of FIGS. 3 and 4;

FIGS. 6A, 6B and 6C illustrate the interval definition of timing anglesin accordance with the present invention for eight-cylinder,six-cylinder, and four-cylinder engines, respectively; and

FIG. 7 shows a wave form chart for an eight-cylinder engin'eillustrating some of the features of the present invention.

Referring to the drawings, FIG. 1 is a simplified block diagram of anaverage engine timer constructed in accordance with the presentinvention. The engine timer generally indicated at 10 comprises a dutycycle generator 12 receiving relatively high frequency electricaloscillations from an oscillator 14 and a reference voltage or currentfrom a DC reference source such as reference source 16. By way ofexample only, oscillator 14 may be a free-running multi-vibratorsupplying continuous square wave pulses to the duty cycle generatorpreferably at a frequency of about 40 kHz. Reference voltage source 16is preferably a regulated DC power supply and has taps providing bothplus and minus volts DC as well as plus 5 volts DC for other portions ofthe circuit. Spark pulses such as indicated at 18 are supplied to dutycycle generator 12 by way of lead 20 and damper pulses such as thatindicated at 22 are supplied to the duty cycle generator over lead 24.The output from duty cycle generator 12 on lead 26 is a train of kHzpulses which have been scaled to have a duty cycle representative ofaverage engine timing as determined by the time of the spark pulses 18in relation to the damper pulses 22. These variable duty cycle pulses onlead 26 are supplied through a low pass RC filter 28 to produce ananalog voltage on lead 30 applied to meter 32 so that the deflection ofthe meter pointer 34 is an indication of average timing for the enginefrom which the spark pulses 18 and damper pulses 22 are derived. Themeter reading is (K 8 )l/360 V (or I) where K is a constant offset, 6 isaverage timing and V is the voltage (or current I) of source 16.

FIG. 2 is a detailed circuit diagram showing the filter 28 and the meter32. The output from the duty cycle generator on lead 26 of FIG. I isapplied as a series of scaling pulses to the input terminal 36 of thefilter 28 of FIG. 2. The circuit comprises a first pair of seriesconnected transistors comprising NPN junction transistor 38 and PNPjunction transistor 40. Connected to the collectors of those twotransistors are the respective bases of a PNP junction transistor 42 anda NPN junction transistor 44. A potentiometer 46 connects the output ofthe transistors to an RC filter network comprising series resistors 48and 50 and shunt capacitors 52 and 54 connected to a positive 15 voltpower supply terminal 56 and similar shunt capacitors 58 and 60connected to a minus 15 volt DC power supply terminal 62. Connectedbetween the output of the filter and ground by a four-pole double-throwswitch 64 is a meter 66. By way of example only, meter 66 may be a 500microammeter having 0-20 full scale deflection of the type manufacturedby Modutec Inc. of Norwalk, Conn. and identified as Model No.ZS-DUA-SOO-NL. Other equivalent voltmeters or ammeters may be utilized.Finally, the filter output is also connected to a positive or negative15 volt DC power supply through a normalizing switch 68.

In operation of the circuit of FIG. 2, transistor 38 is normally biasedon by having its base connected to an intermediate point on voltagedivider 70 in turn coupled to the positive 15 volt DC power supplyterminal 72. Conduction of a transistor 38 forward biases transistor 42causing this latter transistor to turn hard" on. With the reception of apositive pulse at input terminal 36 this positive pulse turns ontransistor 40 in turn turning transistor 44 hard on. The turn on oftransistor 44 causes transistor 38 to be reversed biased turning it offalong with its associated transistor 42. When the positive pulse at theinput terminal 36 disappears transistors 40 and 44 turn off andtransistors 38 and 42 turn back on to assume the initial condition. Thehard saturated switching transistors 42 and 44 apply sharp pulses to thelow pass filter comprising series resistors 48 and 50 and the shuntcapacitors each of which, by way of example only, may have a relativelylarge capacity of about 50 microfarrads. The filter converts the pulsesinto a varying DC or analog signal which is applied across meter 66between terminal 74 and ground. Switch 68 connects terminal 74 either to15 volts, l5 volts, or to ground, as desired.

As previously indicated most automotive engines are timed in the advancemode; that is, they are timed to fire approximately 6 before the topdead-center of the piston. However, some engines are operated in aretard mode where the engine fires after the piston has crossed the topdeadcenter position. Switch 64 makes it possible to operate meter 66 ineither an advance or retard mode by reversing the connections to themeter by movement of the ganged switch blades 76 and 78 between theadvance and retard contacts as illustrated in FIG. 2.

FIG. 3 is a more detailed block diagram of the portions of the averagetimer 10 of the present invention associated with the duty cyclegenerator 12. Like parts in FIG. 3 bear like reference numerals. Adamper pickup illustrated at 80 passes electrical damper signals 22 to aspark counter 82 by way of a damper signal processer 84. Similarly, aspark signal pickup illustrated at 86 passes spark pulses 18 to thespark counter 82 by way of a spark signal processer 88. If desired, atachometer may be coupled to the output of the spark signal processer 88by a lead 92. The tachometer 90 is provided to indicate engine rpm. Byway of example only, the two pickups and the two signal processers alongwith the tachometer 90 may be of the type more fully shown and describedin assignees copending application Ser. No. 219,416 filed Jan. 20, 1972.Pickups 80 and 86 may be constructed in any suitable fashion. Damperpickup 80 is preferably an eddy-current or other magnetic fieldsensitive device while spark pickup 86 is either a magnetic field orelectric field sensitive (capacitive) device as desired. The damperpickup operates as a proximity sensor to produce an output signal onceper revolution of the damper as a notch cut in its periphery passesthrough the pickup field of view. To this end, there is advantageouslypro- 'vided a mounting fixture (not shown) on the engine to support thepickup in suitable relation to the damper so that the pickup senses thenotch as the damper rotates. The mounting fixture may be of any suitableconstruction and does not constitute part of this invention as such.However, it will be realized that placement of the fixture depends onthe availability of an accessible mounting space. Any suitable mountingposition may be employed.

Damper signal processer 84 converts the pickup output into a narrowpulse defining the center of the damper notch thereby providing aprecise reference for generation of damper pulses from which timingmeasurement is made. Spark pickup 86 operates to provide a signalrepresenting the magnetic field pattern associated with the spark coiloutput. In one preferred construction, the spark pickup is attachedaround the spark coil output wire, in the manner of a clip on typeammeter, but other constructions may be employed if desired.

Spark signal processer 88 responds to the pickup output to generate apulse in precise time relationship with the opening of the distributorpoints. This signal is supplied to the spark counter 82 and totachometer 90 which produces an analog signal representative of thefrequency of the spark pickup output. Analog signal generation in thetachometer is accomplished by integrating a series of pulses produced byspark signal processer 88. The tachometer is preferably provided with athree-position switch (not shown) to provide for an eight-, sixandfour-cylinder engine respectively in which the number of sparks perrevolution of the engine are different.

The duty cycle generator 12 of FIG. 1 is made up of the spark counter82, a variable modulous counter 94, a selection network 96, and athree-position switch 98, having four-, six-, and eight-cylindercontacts. The wiper 100 of switch 98 is moved to the appropriate contactmanually in accordance with whether a four-, six-, or eight-cylinderengine is under test. Spark counter 82 is a decade counter which istriggered with each spark signal 18 and which is reset by each dampersignal 22. That is, spark counter 18 produces an output which isrepresentative of the number of spark signals 18 between damper signals22. As previously indicated, on an eight-cylinder engine there arenormally four spark signals per damper signal, for a six-cylinder enginethere are normally three spark signals per damper signal, and for afour-cylinder engine there are normally two spark signals per dampersignal. Variable modulous counter 94 is a divider which divides thesignals from oscillator 14 by a variable amount depending upon theposition of switch 98. When the wiper 100 of switch 98 is on thefour-cylinder contact, variable modulous counter 94 divides by two. Whenswitch 98 is set to the six-cylinder contact variable modulous counter94 divides by three, and when switch 98 is manually set to theeight-cylinder contact variable modulous counter 94 divides by four.Selection network 96 is a variable gating network which passes onlycertain ones of the high frequency pulses from the variable modulouscounter 94. Selection network 96 provides scaling factors to the pulseoutput supplied to the filter in accordance with the count of sparkcounter 82. These scaling factors are based upon the definition ofaverage timing more fully described below.

FIG. 4 is a more detailed block diagram of the portions of the circuitassociated with the variable duty cycle generator 12. Again, like partsbear like reference numerals in FIG. 4. In FIG. 4 the three-positionswitch 98 is connected to the variable modulous counter 94 by a pair ofinvertors 104 and 106. The four-cylinder contact of the switch isconnected to the regulated 15 volt DC power supply through a resistor108 and the six-cylinder contact of the switch is similarly connected tothe 15 volt DC power supply through a resistor 110. When movable contact100 is moved to the four-cylinder contact, the input of invertor 104 isgrounded. Similarly, when switch blade 100 is moved to the six-cylindercontact, the input of invertor 106 is grounded. When the switch is movedto the eight-cylinder contact, neither invertor input is grounded.

Variable modulous counter 94 comprises four NAND gates formed from a7400 integrated circuit and labeled 112, 114, 116 and 118. The NANDgates are connected to a pair of J K flip-flops 120 and 122 through ANDgates 124, 126, 128 and 130 formed from a 7472 integrated circuit asillustrated. Spark counter 82 comprises a binary counter formed from a7490 integrated circuit and is connected to the spark and damperprocessers to receive the spark signal 18 and the damper signal 22, thelatter through a pair of AND gates 132 and 134. The binary counter isillustrated by the box136.

Selection network 96 is a logic network formed from a 7410 and a 7400integrated circuit. It comprises NAND gates 138, 140, 142, 144 and 146.These gates are connected to the output of the variable modulous counter94 and receive signals from spark counter 82 by way of three leads 148,and 152 labeled B, C

and D, respectively, at the outputs of counter 136.

The operation of the timer of the present invention is based upon thefollowing mathematical description of average timing.

Assume the engine rotation is divided into sections where N the numberof pistons in the engine (4, 6, 8). If top dead-center piston is definedas 0, then the section lines fall at L(360)/N/2 L=0, I (N-l i.e.,

If the deviation from these section lines of the appropriate pistonfirings is defined as 8 M 1 N; then the average timing is (AAVE) (1) Aspreviously indicated, the spark counter 82 is a decade counter (7490)which counts on the leading edge of each synchronized spark pulse 18 andreturns to 000 on the synchronized damper pulse 22. FIG. shows thetiming relationship between the spark and damper pulses for eight-,sixand four-cylinder engines. For ease of understanding the spark anddamper pulses are illustrated with the same polarity, it beingunderstood that the damper pulse is conventionally a positive goingpulse and the spark pulses are negative going pulses. As illustrated inFIG. 5 for an eight-cylinder engine there are customarily four sparkpulses 18 for each damper pulse 22; for a six-cylinder engine there arecustomarily three spark pulses 18 for each damper pulse 22, and for afour-cylinder engine there are customarily two spark pulses 18 for eachdamper pulse 22. The count pattern for spark counter 82 is illustratedbeneath each of the wave forms in FIG. 5 with the outputs B, C and D ofthe counter of FIG. 4 illustrated after each damper pulse and after eachspark pulse. For example, referring to the diagram in FIG. 5 for theeight-cylinder engine, after the damper pulse 22 the outputs B, C and Dare all zero. After the first spark pulse the outputs are 100 indicatinga binary 1. After the second spark pulse 18, output B is 0, output C isl, and output D is 0, indicat ing a binary 2. After the third sparkpulse, output B is 1, output C is l, and output D is zero, indicating abinary 3. After the fourth spark pulse output B is zero, output C iszero, and output D is 1, indicating the binary 4. After the seconddamper pulse the outputs are all reset to zero. The B, C and D outputsof the spark counter for the six-cylinder and four-cylinder enginesfollow the same binary numerical order. The highest number counted foran eight-cylinder engine is binary 100 or a decimal 4, for asix-cylinder engine binary O1 1 or decimal 3, and for a four-cylinderengine binary 010 or decimal 2. The least significant bit is output B,the next significant bit is output C, and the most significant bit isoutput D.

Variable modulous counter 94 and selection network 96 constitute scalingcircuits for modifying the number of output pulses passed fromoscillator 14. The scaling logic is based on a modified mathematicaldefinition of average timing in which the engine or damper revolution isdivided into angular intervals. For an eightcylinder engine a revolutionis divided into five inter vals labeled I through 1 For a six-cylinderengine one revolution is divided into four intervals labeled I through1,, and for a four-cylinder engine a revolution is divided into threeangular intervals, labeled I, through I The scaling logic is based onthe modified mathematical definition of an average timing in which:

AVE E X where 8,, V5 average timing M timing with respect to cylinder MX number of cylinders 2.

FIG. 6A illustrates the interval definition of timing angles for aneight-cylinder engine, FIG. 6B for a sixcylinder engine, and FIG. 6C fora four-cylinder engine. Referring to FIG. 6A for the eight-cylinderengine, a revolution is divided into five intervals; namely, a firstinterval of approximately 45; second, third and fourth intervals ofapproximately 90, and a fifth interval of approximately 45. Theintervals I through I differ from 45 and 90, respectively, in that theyare modified by the spark firing deviations 8 through 6 Thus, theintervals for an eight-cylinder engine are exactly defined as follows:

If these intervals are scaled by the formula 4 N =180+i 26m N =l +8 VEwhere N; degree count SAVE average timing angle 4.

Equivalent reasoning is used in the cases of sixcylinder andfour-cylinder engines in which the interval definition of timing anglesare illustrated in FIGS. 6B and 6C, respectively, for sixandfour-cylinders. In FIG. 6B the intervals are defined as follows:

For a four-cylinder engine and referring to FIG. 6C the intervals aredefined as follows:

(equation 3 above). Likewise the counter divides by three for asix-cylinder engine (equation above) and divides by two for afour-cylinder engine (equation 6 above). The modulous of the counter iscontrolled by the gating to the J and K inputs of flip-flops 120 and122. The selection gates 96 scale the outputs Q and Q from flip-flops120 and 122. This scaling is based upon the outputs B, C and D from thespark counter 82. The selection gates obtain the (i-l) factors inequations 3, 5 and 6 above.

The following table gives the scaling logic variables at the modulouscounter outputs Q and Q for an eight-cylinder engine (divide by 4), fora six-cylinder engine (divide by 3), and for a four-cylinder engine(divide by 2):

For an eight-cylinder engine before the first pulse from oscillator 14 Qand Q are both zero. After the first pulse O is at the one level and Ois zero. After the second oscillator pulse both outputs are at the onelevel. After the third pulse Q is zero and Q is 1. After the fourthoscillator pulse both outputs are again at zero. Similar counting cyclesare given in the table for the six-cylinder and four-cylinder modes.

FIG. 7 is a wave form chart for eight-cylinder engine operation. Thespark pulses are shown at 18 and the damper pulses at 22. Again, bothset of pulses are shown with positive polarity for the sake ofcomparison, it being understood that the spark pulses are negative goingpulses as previously indicated. The spacing 7,,- between successivespark pulses for an eightcylinder engine at 1,200 rpm and 00 timing isl2.5 miliseconds. The spacing 'y between damper pulses is 50 milisecondsunder these same conditions. The next wave form illustrated at 154 inFIG. 7 is the B output on lead 148 from spark counder 82. Wave form 156is the C output on lead 150 and wave form 158 is the D output on lead152 of FIG. 4. Wave form 160 is an oscilloscope trace of the scalepulses appearing on output lead 26 as supplied to the filter and thistrace is expanded in the circles 162, 164, 166, 168 and 170 for the fiveintervals 1 through 1;, for eight-cylinder operation. During the firstInterval I illustrated at 162 no scale pulses are passed to the filterwhereas during the succeeding four intervals correspondingly increasednumbers of scale pulses are passed through gate 96 until the fifthinterval in which i 1/4 l and all scale pulses pass to the filter. It isapparent that corresponding conditions apply for the four and threeintervals of the revolution of the engine for the sixand fourcylinderengine operations.

It is apparent from the above, that the present invention provides animproved average engine timer and particularly one that is of simplifiedand inexpensive construction and which may be used with a small initialinvestment in average engine timing equipment. Important features of thepresent invention include the provision of a variable duty cyclegenerator for varying the duty cycle of relatively high frequency pulsesin accordance with average engine timing. These variable duty cyclepulses are applied through a filter to create an analog signal which maybe used to drive an analog indicator such as a conventional voltmeter orammeter. Also incorporated in the system is a tachometer for indicatingengine rpm although it is apparent that the timer of the presentinvention is substantially independent of speed and there is nonecessity for closely controlling engine rpm in order to obtain anaccurate reading of average engine timing. The timer may be manuallyswitched so that it operates to indicate average timing for either afour-cylinder, six-cylinder, or an eightcylinder engine. In addition,the timer incorporates an advance-retard switch so that average enginetiming may be indicated either in the advance or retard mode. Ifdesired, the output from filter 28 may be applied through an analog todigital converter to a digital counter or the like to provide a digitaldisplay of engine timing.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The presentembodiment is therefore to be considered in all respects as illustrativeand not restrictive, the scope of the invention being indicated by theappended claims rather than by the foregoing description, and allchanges which come within the meaning and range of equivalency of theclaims are therefore intended to be embraced therein.

I claim:

1. An average timer for multicylinder internal combustion enginescomprising a first input terminal for receiving a signal indicative of apredetermined angular position of the engine crankshaft during eachrevolution of an engine under test, a second input terminal forreceiving a signal indicative of the time of firing of each spark plugof an engine under test, two successive sig nals at said first inputterminal defining a first longer time interval, the successive signalsat said second input terminal within said first time interval definingin combination with said successive signals at said first input terminala series of shorter time intervals within each longer time interval, anoscillator, a duty cycle generator coupled to both said input terminalsand to said oscillator, said duty cycle generator modifying theoscillator signals to produce an electrical output which has a differentduty cycle for each of said shorter time intervals in a longer timeinterval, a detector'coupled to said duty cycle generator for producingan analog signal representative of the duty cycle of the output fromsaid generator, and means for coupling a display to the output of saiddetector.

2. A timer according to claim 1 wherein said detector comprises a lowpass filter.

3. A timer according to claim 2 wherein said duty cycle generatorcomprises a variable modulus counter and a selection network including aplurality of logic gates for gating the pulses passed from said variablemodulus counter to said filter.

4. A timer according to claim 3 wherein said counter includes means fordividing by four, means for dividing by three and means for dividing bytwo.

5. A timer according to claim 3 wherein said duty cycle generatorfurther comprises a spark counter coupled between said terminals andsaid selection network for controlling said selection network inaccordance with the time difference between the signals received at saidterminals.

6. A timer according to claim 5 wherein said spark counter supplies adifferent signal to said selection network with the receipt of eachsignal from either one of said terminals during a revolution of anengine under test.

7. A timer according to claim 6 wherein said spark counter is triggeredby the signal from said second terminal and reset by the signal fromsaid first terminal.

8. An average timer for multicylinder internal combustion enginescomprising a damper pick up for producing impulses indicative of apredetermined angular position of the engine crankshaft during eachrevolution of an engine under test, a spark pick up for producingimpulses indicative of the firing of each spark plug of an engine undertest, a pulse oscillator, a divider coupled to the output of saidoscillator, said divider including means for dividing the number ofoutput pulses from said oscillator by a factor dependent upon the numberof cylinders in an engine under test, a selection network including aplurality of logic gates coupled to the output of said divider forpassing selected pulses from said divider, a spark counter coupling saiddamper and spark pickups to said selection network for controlling saidselection network in accordance with the time relationship between theimpulses from said pickups, a low pass filter coupled to the output ofsaid selection network, and display means coupled to the output of saidfilter.

9. A timer according to claim 8 wherein said display means comprises ananalog display.

10. A timer according to claim 9 wherein said display comprises a meterwith a movable pointer.

11. A timer according to claim 10 wherein said meter is coupled to saidfilter by an advance-retard switch whereby either advance or retardengine firing may be displayed on said meter.

12. A timer according to claim 8 wherein said spark counter supplies afirst output to said selection network for a first interval between adamper impulse and the first spark impulse of an engine revolution, adifferent output for each interval between successive spark impulses ofsaid engine revolution, and a still different output for the intervalbetween the last spark impulse of said revolution and the next damperimpulse.

13. A timer according to claim 12 wherein said selection network passesincreasing proportions of the pulses from said divider with each of thesuccessive intervals of said revolution.

14. A timer according to claim 13 wherein said selection network passesno pulses from said divider during the first interval of said revolutionand all the pulses from said divider during the last interval of saidrevolution.

15. A method of determining average engine timing in a multicylinderengine comprising generating a series of pulses, detecting each enginedamper and spark impulse for each revolution of an engine under test,scaling the series of pulses to produce an output having a differentduty cycle for each time interval between successive damper and sparkimpulses in a single revolution of the engine, and producing an analogsignal proportional to the duty cycle of the scaled pulses.

16. A method according to claim 15 wherein said pulses are also scaledin accordance with the number of cylinders in the engine under test.

17. A method according to claim 16 wherein said pulses are scaledaccording to the formula:

where S average timing 6 timing with respect to cylinder M X number ofengine cylinders 2.

18. A method according to claim 17 wherein X may have any of the valuesselected from the group consisting of two, three and four.

904050 UNHED STATES PATENT OFFICE (5/59) I a v QETIFICATE 0F CORRECTIONPatent 3 @832 .6118 Dated A gust 27 1974 Inv n fl Joseph R. PnttQhanm Itis certified that error appears in the above-ideutified patent and thatsaid Letters Patent are hereby corrected as shown below:

In Col. 2, line 2, "imperfections" should vread imperfections-=0 V InCola a, line 23, (formula 4', bottom line); "o 1" should read m l-- InCol. 12, line 34, (formula, bottom line) "n 1" should read -m l---Signed and sealed this Sth-day of November 1974.

(SEAL) Q Attest: McCOY MI. GIBSON JR. c. MARSAHLL DANN Attestlng OfficerCommissioner of Patents

1. An average timer for multicylinder internal combustion enginescomprising a first input terminal for receiving a signal indicative of apredetermined angular position of the engine crankshaft during eachrevolution of an engine under test, a second input terminal forreceiving a signal indicative of the time of firing of each spark plugof an engine under test, two successive signals at said first inputterminal defining a first longer time interval, the successive signalsat said second input terminal within said first time interval definingin combination with said successive signals at said first input terminala series of shorter time intervals within each longer time interval, anoscillator, a duty cycle generator coupled to both said input terminalsand to said oscillator, said duty cycle generator modifying theoscillator signals to produce an electrical output which has a differentduty cycle for each of said shorter time intervals in a longer timeinterval, a detector coupled to said duty cycle generator for producingan analog signal representative of the duty cycle of the output fromsaid generator, and means for coupling a display to the output of saiddetector.
 2. A timer according to claim 1 wherein said detectorcomprises a low pass filter.
 3. A timer according to claim 2 whereinsaid duty cycle generator comprises a variable modulus counter and aselection network including a plurality of logic gates for gating thepulses passed from said variable modulus counter to said filter.
 4. Atimer according to claim 3 wherein said counter includes means fordividing by four, means for dividing by three and means for dividing bytwo.
 5. A timer according to claim 3 wherein said duty cycle generatorfurther comprises a spark counter coupled between said terminals andsaid selection network for controlling said selection network inaccordance with the time difference between the signals received at saidterminals.
 6. A timer according to claim 5 wherein said spark countersupplies a different signal to said selection network with the receiptof each signal from either one of said terminals during a revolution ofan engine under test.
 7. A timer according to claim 6 wherein said sparkcounter is triggered by the signal from said second terminal and resetby the signal from said first terminal.
 8. An average timer formulticylinder internal combustion engines comprising a damper pick upfor producing impulses indicative of a predetermined angular position ofthe engine crankshaft during each revolution of an engine under test, aspark pick up for producing impulses indicative of the firing of eachspark plug of an engine under test, a pulse oscillator, a dividercoupled to the output of said oscillator, said divider including meansfor dividing the number of output pulses from said oscillator by afactor dependent upon the number of cylinders in an engine under test, aselection network including a plurality of logic gates coupled to theoutput of said divider for passing selected pulses from said divider, aspark counter coupling said damper and spark pickups to said selectionnetwork for controlling said selection network in accordance with thetime relationship between the impulses from said pickups, a low passfilter coupled to the output of said selection network, and displaymeans coupled to the output of said filter.
 9. A timer according toclaim 8 wherein said display means comprises an analog display.
 10. Atimer according to claim 9 wherein said dIsplay comprises a meter with amovable pointer.
 11. A timer according to claim 10 wherein said meter iscoupled to said filter by an advance-retard switch whereby eitheradvance or retard engine firing may be displayed on said meter.
 12. Atimer according to claim 8 wherein said spark counter supplies a firstoutput to said selection network for a first interval between a damperimpulse and the first spark impulse of an engine revolution, a differentoutput for each interval between successive spark impulses of saidengine revolution, and a still different output for the interval betweenthe last spark impulse of said revolution and the next damper impulse.13. A timer according to claim 12 wherein said selection network passesincreasing proportions of the pulses from said divider with each of thesuccessive intervals of said revolution.
 14. A timer according to claim13 wherein said selection network passes no pulses from said dividerduring the first interval of said revolution and all the pulses fromsaid divider during the last interval of said revolution.
 15. A methodof determining average engine timing in a multicylinder enginecomprising generating a series of pulses, detecting each engine damperand spark impulse for each revolution of an engine under test, scalingthe series of pulses to produce an output having a different duty cyclefor each time interval between successive damper and spark impulses in asingle revolution of the engine, and producing an analog signalproportional to the duty cycle of the scaled pulses.
 16. A methodaccording to claim 15 wherein said pulses are also scaled in accordancewith the number of cylinders in the engine under test.
 17. A methodaccording to claim 16 wherein said pulses are scaled according to theformula:
 18. A method according to claim 17 wherein X may have any ofthe values selected from the group consisting of two, three and four.